A typical modern computer system includes a microprocessor, memory, and peripheral computer resources, i.e., monitor, keyboard, software programs, etc. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions from a computer program.
FIG. 1 shows a prior art diagram of an example of a computer system that has a display unit (2), user input (12), external memory (8), internal memory (6), a central processing unit (CPU) (4), and a texture engine (10). The display unit (2), user input (12), and external memory (8) are external components, while the CPU (4), texture engine (10), and internal memory (6) are internal components (14). The CPU (4) and texture engine (10) are also parts of the arithmetic, logic, and control circuitry of the microprocessor.
One goal of the computer system is to execute instructions provided by the computer's users and software programs. The execution of instructions is carried out by the CPU (4). Data needed by the CPU (4) to carry out an instruction is fetched from the external memory (8) and copied into the internal memory (6). The CPU (4) normally uses the data copies to carry out an instruction rather than the original data because, in many cases, the microprocessor can access the internal memory (6) more quickly than the external memory (8).
The texture engine (10) interpolates and maps data that allows the display unit (2) to display graphical images with textured surfaces. FIG. 2 shows how texture instructions and texture data flow through the computer system when a texture is constructed for a graphical image. When the CPU (4) receives input telling it to construct a particular graphical image, the CPU (4) sends texture calculation commands (16) to the texture engine (10). The texture engine uses the texture calculation commands (16) to determine what texture write data (20) to send to the internal memory (6). The texture write data (20) tells the internal memory what texture gradients, colors, etc. to send back to the texture engine (10) in the texture read response (22). Next, the texture engine (10) interpolates, or maps, the texture read response (22) into texture display data (18). The texture display data (18) is used by the CPU (4) to construct texture display commands (24). The texture display commands (24) tell the display unit (2) how to display the graphical image.
The texture engine (10) interacts with the internal memory (6) through an input/output port called an interface (26). Because the texture engine (10) performs several calculations to produce each image, the rate at which it sends and receives data through the interface (26) is critical in determining the amount of time it will take to display a graphical image. As a result, the rate at which the interface (26) between the texture engine (10) and the internal memory (6) propagates data is a primary concern. The rate at which the texture engine propagates data is also known as the speed of the interface (26). The speed of the interface (26) is determined by the interface's (26) type and construction.
A prior art interface is illustrated in FIG. 3. This type of interface is called a clock forwarding interface. In order for a clock forwarding interface to operate correctly, each device that accepts input from the interface (26), also called a client device, must emit a forwarded clock. Referring to FIG. 3, a FBC3 (28) is an application-specific integrated circuit (ASIC) that features a texture engine (10), while an SDRAM (30) is a component of the internal memory (6). The FBC3 (28) propagates write data (32) and a forwarded clock (34) to the SDRAM (30) along a write path (38). The forwarded clock (34) is in sync with the FBC3's core clock. Next, the SDRAM (30) propagates read data (36) to the FBC3 (28) along a read path (40).
Because the SDRAM (30) is a globally synchronous device, it cannot emit its own forwarded clock. However, because a clock forwarding interface requires that each client device emit a forwarded clock, the SDRAM (30) emits an imaginary clock, also known as a virtual clock. The time phase of the virtual clock is perceived through the phase of the read data (36).